Here is another possible chip configuration. Each box represents one WIZ. The tiny rectangles inside each box represent registers on its bus, each with a backend function (not shown). Only a portion of the bus and a few registers are shown, and only a portion of the full chip is shown. But you get the idea.

Each WIZ can have a different number of registers and a different variety of backend objects. WIZes may vary in size from a few thousand to a few million transistors each. Thus while the above diagram looks neat and tidy, in reality we may have many varying sizes of WIZes in many shapes. This rectangular array is an idealized picture.

The chip itself can be manufactured at any size and can have as many WIZes as it can hold, from as few as a dozen to as many as a million or more.

Each WIZ can run independently, with its own executor copying across its own bus between its own backend devices. And all the WIZes on the chip can run simultaneously, in parallel, creating the possibility of massively parallel chip-scale operations.