Quite a few chapters ago (in "The frontend") I introduced the WIZ "Executor", as above. The executor merely takes the incoming instruction word (here shown as a 16-bit instruction with 8 bits of source address and 8 bits of destination address), latches it, and drives the instruction lines on the main WIZ bus, along with generating the copy start signal. The source register's RCL will see those bits and the instruction cycle will begin.

On the left side above it says "incoming instruction word [0:15]. Until now, that external source of instruction words has remained mysterious.

First note, we are a Harvard architecture: our instruction memory is distinct from our attached RAM or RAMs.

Secondly note, the ZOZ splits programs into fragments. That means that typical sequences will be very short.

Also note that WIZ sequences only run forward. (See chapter "Conditional skip"). Thus we need a "streaming" memory more than a random access memory. We only need to be able to reset it to start streaming at the first instruction word, and continue to deliver words in sequence until reaching the end.

And finally note that on a WIZ with 256 registers we need an 8-bit bus address and therefore a 16-bit instruction word. But on a WIZ with less than 128 registers in use, we can have a 7-bit address and a 14-bit instruction word. As the ZOZ translates instructions (from pairs of long serial numbers to pairs of short bus addresses) into each WIZ as it downloads them, this creates no compatibility problems at all. Indeed, a "bare naked" WIZ may operate on less than 16 registers and have an 8-bit instruction word.

Thus, we will very typically need very little instruction memory. On average, perhaps 20 words of 16-bit instruction would be more than enough. Half that for a naked WIZ (which may be very common).

On a chip of many WIZes, some will have more instruction memory and some less, and the ZOZ will choose to download sequences into WIZes with the appropriate amount. If a sequence is too big for any available WIZ, it can easily be split into two pieces and implemented on two WIZes.

A small register file or any sort of shift register would work fine. (And be far faster than L1 cache, by the way). I imagine a typical implementation for N words K-bits wide to be K shift registers all N bits long, connected to the K "incoming instruction word [0:K]" inputs of the executor.

Bottom line: we have a great flexibility of implementation for our code memory.