RAM IP blocks are readily available. We don't need to do any special design here. This is true of many kinds of IP blocks which already use a register-based interface, eg disk controller, motor controller, radio interface, and much more. There is not much then to adapt almost any such IP to become WIZ backend devices.

To interface a RAM, we could have two frontend registers, data and address. We store a number into the address register and read/write the RAM's data at that address.

Various RAM IPs have various control signals. A tiny bit of "glue" logic would convert them into what we need, the backend read-ready and write-ready, etc. We'd tap into EN-IN and EN-OUT to see when the frontend was active, and convert them into RAM control signals to do the required operations.

Generally, RAM IP blocks already work this way, and there may be almost no glue needed here.

The RAM IP may also provide its own internal cache. This would be transparent to our Frontend operation. Other features like auto-increment of the address register, and lower and upper bounds protection could be imlemented. These could be brought out to more WIZ frontend registers if desired (eg, "lower bound", "upper bound").